Random access memories have been devised uitlizing metal-oxide-semiconductor field effect transistors (MOSFET) or other conductor-insulator-semiconductor field effect transistor integrated circuit technology. Random access memories can be formed from a large number of integrated semiconductor circuit chips each having a large number of binary data storage cells. Such memories have used binary bit storage cells comprised of several MOS transistors connected as a flip-flop to provide a static memory. Because of the relative complexity, size and power requirements of these static memory cells, random access memories utilizing dynamic storage cells with a smaller number of MOS transistors have been devised. The static type of memory cell includes cross coupled transistor stages wherein one or more paths to ground can be selectively switched on or off. In the dynamic type of memory cell, a charge is stored on a capacitor by operation of one or more transistors.
The time required to retrieve a particular bit of data from a random access memory, commonly referred to as the access time, is a critical factor in such memory systems. In accessing or reading static type cells, the column bus may be discharged substantially to zero by currents passing through the memory cell in order to detect a logic "zero" stored in the cell. In the systems utilizing dynamic memory cells which have destructive read cycles, data is read from the memory cell by detecting a voltage kick on the column bus as the capacitor of the memory cell is either charged or discharged when addressed. A typical characteristic of the dynamic memory cell is the requirement of a refresh of the cell voltage to maintain the data stored therein or to write data therein. Because the dynamic memory cell is small in size, high packing densities of cells can be achieved with resulting low power consumption of the random access memory. Additionally, dynamic memory cells can be fabricated utilizing a simpler process over the process required for the fabrication of static memory cells. Because of these described advantages and the disadvantages of requiring refresh cycles with the use of dynamic memory cells, self-refreshed dynamic memory cells have been developed. Such a cell operates so that the memory refresh is transparent to the user and the memory appears to be fully static.
In order to improve upon the layout area and power drain of static memory devices, pseudo-static random access memories have been proposed together with self-refreshing circuitry. A self-refreshing cell utilizing five transistors and dynamic sensing is described in a paper by Caywood et al. entitled "A Novel 4 K Static RAM with Submilliwatt Standby Power", IEEE Transactions on Electron Devices, Volume Ed.--26, No. 6, June 1979 at page 861. Such a pseudo-static cell being derived from a one-transistor, one-capacitor dynamic cell concept, causes the readout to be inherently destructive and therefore the cell must be refreshed after each read operation.
A need has thus arisen for an improved clocking system for a self-refreshed dynamic MOS memory cell. A need has further arisen for a self-refreshed dynamic memory cell which can be read in a nondestructive manner, such that the memory refresh is transparent to the user and the memory cell appears fully static.